The present invention relates to a delay circuit, a DLL circuit, and a semiconductor device provided with the DLL circuit.
A delay circuit is one of the constituent circuits of a delay locked loop (DLL: Delay Locked Loop) circuit. High-speed data-transfer technology is essential in the highly advanced information society of today, and progress toward a higher speed is underway even at an interface of a double data rate (DDR) memory using the DLL circuit.
One basic configuration of the delay circuit is a multi-stage switching-type delay circuit. A multi-stage switching-type delay circuit is represented by a method whereby a delay amount is adjusted by switching the number of stages of a gate, and the method has a point in its favor in that the delay amount is proportional to the number of stages. However, there can be the case where a hazard occurs at the time of switching the number of stages.
In Japanese Unexamined Patent Application Publication No. 2005-292947, the number of stages is controlled with two-hot encoding in order to hold back a hazard period to a minimum against hazard occurrence at the time of switching the number of stages. More specifically, a technology has been disclosed whereby a turn-back stage and the next stage are controlled to enable hazard occurrence to be held back so as to correspond only to a delay element that is newly passed through by the switching of the number of stages.